Enhanced microprocessor or microcontroller

ABSTRACT

A microcontroller device has a central processing unit (CPU); a data memory coupled with the CPU divided into a plurality of memory banks, a plurality of special function registers and general purpose registers which may be memory-mapped, wherein at least the following special function registers are memory-mapped to all memory banks a status register, a bank select register, a plurality of indirect memory address registers, a working register, and a program counter high latch; and wherein upon occurrence of a context switch, the CPU is operable to automatically save the content of the status register, the bank select register, the plurality of indirect memory address registers, the working register, and the program counter high latch, and upon return from the context switch restores the content of the status register, the bank select register, the plurality of indirect memory address registers, the working register, and the program counter high latch.

TECHNICAL FIELD

The technical field of the present application relates tomicroprocessors or microcontrollers.

BACKGROUND

Microcontrollers generally constitute a system on a chip and comprise amicroprocessor and a plurality of peripheral components. A wide varietyof such microcontrollers exist having 8-bit, 16-bit and 32-bitarchitecture. Existing microcontrollers such as 8-bit microcontrollersmanufactured by Microchip Technology Inc. provide for a flexiblearchitecture. Such microcontrollers comprise a Harvard architecture inwhich program and data memories are separated. Microcontrollers of thistype further comprise a specific banking system that allows access tothe data memory. Generally, the data memory is divided in a plurality ofbanks and a bank select register defines which of the banks is currentlyselected and accessible. To access other banks, the bank select registerhas to be re-programmed. Even though, a banking scheme, thus, onlyallows access to a defined memory bank, these controllers includeinstructions that force a switch to a predefined bank. This provides forimproved and powerful performance despite the general accesslimitations.

However, there exists still bottlenecks in accessing the memory. Hence,there exists a need for an improved microcontroller architecture.

SUMMARY

According to an embodiment a microprocessor or microcontroller devicemay comprise a central processing unit (CPU); a data memory coupled withthe CPU, wherein the data memory is divided into a plurality of memorybanks; and a plurality of special function registers and general purposeregisters which may be memory-mapped to the data memory, wherein atleast the following special function registers are memory-mapped to allmemory banks: a status register, a bank select register, a plurality ofindirect memory address registers, a working register, and a programcounter high latch; wherein upon occurrence of a context switch, the CPUis operable to automatically save the content of the status register,the bank select register, the plurality of indirect memory addressregisters, the working register, and the program counter high latch, andupon return from the context switch restores the content of the statusregister, the bank select register, the plurality of indirect memoryaddress registers, the working register, and the program counter highlatch.

According to a further embodiment, the device may further comprise aninterrupt unit coupled with the CPU, wherein the context switch may beinduced by an interrupt. According to a further embodiment, the contextswitch may be software induced. According to a further embodiment, thecontent of the status register, the bank select register, the pluralityof indirect memory address registers, the working register, and theprogram counter high latch may be saved to a plurality of additionalregisters. According to a further embodiment, the content of the statusregister, the bank select register, the plurality of indirect memoryaddress registers, the working register, and the program counter highlatch may be saved to a stack or additional memory. According to afurther embodiment, each memory bank may have the following specialfunction registers memory mapped:—a plurality of indirect addressingmode registers which cause an indirect addressing access upon a read orwrite access to the first and second indirect addressing moderegisters;—a first program counter register;—a status register,—aplurality of indirect memory address registers;—a bank selectregister,—a working register,—a program counter high latch register,and—an interrupt control register. According to a further embodiment,the special function registers can be mapped starting at memory bankaddress 0. According to a further embodiment, the device may comprise 2indirect addressing mode registers and 4 indirect memory addressregisters, wherein access to an indirect addressing mode register mayuse 2 concatenated indirect memory address registers of the 4 indirectmemory address registers and wherein the special function registers aremapped from memory bank address 0 to 0Bh. According to a furtherembodiment, the device may further comprise a program memory coupledwith the CPU, wherein a bit in the indirect memory address registersindicates whether an indirect memory access is performed on the datamemory or the program memory.

According to another embodiment, a method of operating a microprocessoror microcontroller device with a central processing unit (CPU); a datamemory coupled with the CPU, wherein the data memory is divided into aplurality of memory banks; a plurality of special function registers andgeneral purpose registers, may comprise the steps of: memory mapping atleast the following special function registers to all memory banks: astatus register, a bank select register, a plurality of indirect memoryaddress registers, a working register, and a program counter high latch;upon occurrence of a context switch, saving automatically the content ofthe status register, the bank select register, the plurality of indirectmemory address registers, the working register, and the program counterhigh latch, and upon return from the context switch restoring thecontent of the status register, the bank select register, the pluralityof indirect memory address registers, the working register, and theprogram counter high latch.

According to a further embodiment, the method may further compriseinducing the context switch by an interrupt. According to a furtherembodiment, the context switch may be software induced. According to afurther embodiment, the content of the status register, the bank selectregister, the plurality of indirect memory address registers, theworking register, and the program counter high latch may be saved to aplurality of additional registers. According to a further embodiment,the content of the status register, the bank select register, theplurality of indirect memory address registers, the working register,and the program counter high latch may be saved to a stack or additionalmemory. According to a further embodiment, each memory bank may have thefollowing special function registers memory mapped:—a plurality ofindirect addressing mode registers which cause an indirect addressingaccess upon a read or write access to the first and second indirectaddressing mode registers;—a first program counter register;—a statusregister,—a plurality of indirect memory address registers;—a bankselect register,—a working register,—a program counter high latchregister, and—an interrupt control register. According to a furtherembodiment, the special function registers can be mapped starting atmemory bank address 0. According to a further embodiment, the method mayuse 2 indirect addressing mode registers and 4 indirect memory addressregisters, wherein access to an indirect addressing mode register uses 2concatenated indirect memory address registers of the 4 indirect memoryaddress registers and wherein the special function registers are mappedfrom memory bank address 0 to 0Bh. According to a further embodiment,the method may further use a program memory coupled with the CPU,wherein a bit in the indirect memory address registers indicates whetheran indirect memory access is performed on the data memory or the programmemory.

Other technical advantages of the present disclosure will be readilyapparent to one skilled in the art from the following figures,descriptions, and claims. Various embodiments of the present applicationmay obtain only a subset of the advantages set forth. No one advantageis critical to the embodiments.

BRIEF DESCRIPTION OF THE DRAWINGS

A more complete understanding of the present disclosure and advantagesthereof may be acquired by referring to the following description takenin conjunction with the accompanying drawings, in which like referencenumbers indicate like features, and wherein:

FIG. 1 shows a block diagram of microcontroller architecture accordingto an embodiment.

FIG. 2 shows an embodiment of a program counter and its coupling to aninternal bus.

FIGS. 3-6 show different operations on the program counter depending onthe instruction being executed.

FIG. 7 shows an embodiment of a stack and control logic.

FIG. 8 shows an embodiment of a program memory map and stack.

FIG. 9 shows an embodiment of a bank select register.

FIG. 10 shows an embodiment of the structure of a memory bank in thedata memory.

FIG. 11 shows an access scheme for indirect memory access.

FIG. 12 is a table showing the special function register summaryaccording to an embodiment.

FIGS. 13A and B are a table showing the instruction set of amicroprocessor or microcontroller according to an embodiment.

While embodiments of this disclosure have been depicted, described, andare defined by reference to example embodiments of the disclosure, suchreferences do not imply a limitation on the disclosure, and no suchlimitation is to be inferred. The subject matter disclosed is capable ofconsiderable modification, alteration, and equivalents in form andfunction, as will occur to those ordinarily skilled in the pertinent artand having the benefit of this disclosure. The depicted and describedembodiments of this disclosure are examples only, and are not exhaustiveof the scope of the disclosure.

DETAILED DESCRIPTION

FIG. 1 shows amongst others different functional units of a centralprocessing unit of a microprocessor or microcontroller relevant foraccessing program and data memory in a Harvard-type architectureaccording to an embodiment. An instruction register 110 may store afetched instruction which may be decoded by a control logic 130. Aplurality of indirect addressing registers 150 may be provided eachstoring an address. Even though shown separately in FIG. 1, these andother special function registers are part of a special function registerblock 185. To perform an indirect addressing access, a read or write toa dedicated special function register in special function register block185 is performed. In case such an indirect addressing access isexecuted, control logic 130 controls a multiplexer 140 which receives onthe input side an address from indirect address register 150. Accordingto an embodiment, the indirect address registers have a predefined bit,such as the most significant bit, which is decoded by control logic 130to determine whether an indirect access to program memory 120 or to datamemory 160 will be performed.

In an 8-bit architecture, the data memory is 8-bit wide. According tothe Harvard architecture, the program memory is separated from the datamemory and may have a different size. For example, in one embodiment,the program memory may be 14, 15 or 16 bits wide. Thus, instructions canbe decoded that include for example, an 8 bit direct address. Someinstruction may contain even more address bits that may be combined withanother register to perform, for example, relative addressing.

The data memory 160 may be divided into a plurality of banks that can bedecoded by 7 or 8 bits. Each bank can be considered as a register file.According to one embodiment, data memory contains a total of 16 bankseach having 256 addressable memory locations resulting in a total memoryof 4096 bytes. According to another embodiment, 16 banks with 128addressable memory locations may be provided. Other configurations arepossible according to various embodiments. The central processing unitmay further include an arithmetic logic unit 170 (ALU) coupled with aworking register 180. Working register 180 is one of a plurality ofspecial function registers of block 185. As stated above, data memory160 may be divided into a plurality of banks 1 . . . n. With theexception of certain addressing modes, instructions generally have onlyaccess to the selected memory bank. Thus, certain important specialfunction registers from special function register block 185 are memorymapped to all memory banks 1 . . . n as indicated by the arrow betweendata memory 160 and special function register block 185. According tovarious embodiments, special function registers not mapped to all memorybanks may be mapped to a single memory bank at respective differentmemory locations. According to various embodiments, some specialfunction registers may not be mapped to memory at all.

Even though the mapping of certain special function registers to allmemory banks limits the accessible free RAM in each memory bank, manyotherwise necessary bank switch sequences can be avoided to accessimportant special function register. For example, a microcontroller mayhave 12 special function registers such as the working register 180mapped to all memory banks Thus, according to an embodiment, each memorybank may have 244 or 116 free memory locations depending on the size ofeach memory bank. Other configurations are possible according to variousembodiments.

According to an embodiment, the enhanced microcontroller may contain an8-bit ALU 170 and working register 180 (WREG). The ALU 170 may be ageneral purpose arithmetic unit. It performs arithmetic and Booleanfunctions between data in the working register 180 and any registerfile. The ALU 170 can be 8-bits wide and may be capable of addition,subtraction, shift, and logical operations. Unless otherwise mentioned,arithmetic operations may be two's complement in nature. WREG 180 may bean 8-bit working register used for ALU operations. The WREG register 180is addressable and can be directly written or read. According to anembodiment, WREG 180 is one of the 12 common SFR's that are mapped toall 16 banks—its address may be for example 09h. The Arithmetic andLogic Unit 170 may be capable of carrying out arithmetic or logicaloperations on two operands or a single operand. All single operandinstructions operate either on the WREG register 180 or the given fileregister. For two operand instructions, one of the operands is the WREGregister 180 and the other one is either a file register or an 8-bitimmediate constant. Depending on the instruction executed, the ALU 170may affect the values of the Carry (C), Digit Carry (DC) or Zero (Z)bits in the STATUS register 190. The C and DC bits operate as a borrowand digit borrow out bit, respectively, in subtraction. Examplesaffecting these status bits are such instructions as SUBLW and SUBWF aswill be explained in more detail below.

The STATUS register 190, as shown in FIG. 1 may contain: Arithmeticstatus of the ALU such as carry/borrow, digit carry/borrow, and zeroflag; RP<1:0>, representing the lower two bank select; bits for directaddressing; IRP, representing the bank select register bit for indirectaddressing; time out bit, and power down bit.

According to an embodiment, the enhanced microcontroller comprises aBank Select Register (BSR), in order to maintain backwardscompatibility, also bits RP<1:0> may be maintained. There may be full,bi-directional mirroring between RP<1:0> and BSR<1:0>: changing the oneregister, therefore, automatically changes the other. Hence, RP<1:0> andBSR<1:0> point to the same physical memory.

Even though the enhanced microcontroller contains multiple full indirectaddress registers 150 (file select registers (FSR's)), bit IRP may bealso maintained for backwards compatability—it is a direct,bi-directional mirror of FSR0H<0>. Changing FSR0H<0>, thus,automatically changes IRP, and visa versa. IRP and FSRH0h<0> point tothe same physical memory.

According to an embodiment, the STATUS register 190 is common across allbanks, and can be located at 03h. Fast context saving on interrupts, aswill be explained in more detail below, is implemented for all theSTATUS bits, except TO and PD. The STATUS register can be thedestination for any instruction, like any other register. If the STATUSregister is the destination for an instruction that affects the Z, DC orC bits, then these bits are set or cleared according to the devicelogic. Furthermore, the TO and PD bits are not writable. Therefore, theresult of an instruction with the Status register 190 as destination maybe different than intended. For example, the instruction CLRF STATUSwill clear all the bits except TO and PD, and then the Z bit willautomatically be set by device logic. This leaves the STATUS register190 as ‘000u u100’ (where u=unchanged). The C and DC bits operate as aBorrow and Digit Borrow out bit, respectively, in subtraction.

The status register 190 thus may contain the following bits:

IRP: Indirect Register Bank Select bit (For backwards compatability.Mirrors FSR0H<0>) 1=Bank 2, 3 (100h-1FFh); 0=Bank 0, 1 (00h-FFh)

RP<1:0>: Register Bank Select bits (For backwards compatability. MirrorsBSR<1:0>) 00=Bank 0 (00h-7Fh); 01=Bank 1 (80h-FFh); 10=Bank 2(100h-17Fh); 11=Bank 3 (180h-1FFh)

TO: Time-out bit (Not automatically saved on interrupts) 1=Afterpower-up, CLRWDT instruction or SLEEP instruction; 0=A watch dog timertime-out occurred;

PD: Power-down bit (Not automatically saved on interrupts) 1=Afterpower-up or by the CLRWDT instruction; 0=By execution of the SLEEPinstruction

Z: Zero bit: 1=The result of an arithmetic or logic operation is zero;0=The result of an arithmetic or logic operation is not zero.

DC: Digit Carry/Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions):1=A carry-out from the 4th low-order bit of the result occurred; 0=Nocarry-out from the 4th low-order bit of the result.

C: Carry/Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions): 1=Acarry-out from the Most Significant bit of the result occurred; 0=Nocarry-out from the Most Significant bit of the result occurred.

For Borrow, the polarity can be reversed. A subtraction is executed byadding the two's complement of the second operand. For rotate (RRF, RLF)instructions, this bit is loaded with either the high or low-order bitof the source register.

The enhanced microcontroller core can directly or indirectly address itsregister files (banks) or data memory. According to an embodiment, allspecial function registers, including the Program Counter (PC) andWorking Register (WREG), are mapped in the data memory. The enhancedmicrocontroller core has an orthogonal (symmetrical) instruction setthat makes it possible to carry out any operation on any register usingany addressing mode. This symmetrical nature and lack of ‘specialoptimal situations’ make programming with the enhanced microcontrollercore simple yet efficient. In addition, the learning curve for a user isreduced significantly.

According to an embodiment, the following blocks may be realized in thecore: Program counter; Instruction decode; ALU; read only memory (ROM)Latch/IR Latch; FSRs and address generation logic; Working Register;WREG; Status bits in STATUS; Interrupt vectoring control; with fastcontext saving; The bank select register BSR.

The following blocks may not be considered part of the CPU: The stack;Reset generation circuitry (watch dog timer (WDT), power on reset (POR),brown out reset (BOR), etc.); Program Memory; Peripherals; RAM; RAMAddress Control; Q-clock generator and control; Interrupt Enable andFlagging; interrupt control registers; Configuration bits; Device IDword; ID locations; Clock drivers.

As stated above, according to an embodiment, the following registers maybe common across all 16 banks: INDF0 (Used for indirect addressing andmay not be a physical register); INDF1 (Used for indirect addressing andmay not be a physical register); PCL (PC LSB); STATUS; FSR0L (Indirectmemory address 0, LSB); FSR0H (Indirect memory address 0, MSB); FSR1L(Indirect memory address 1, LSB); FSR1H (Indirect memory address 1,MSB); WREG, the working register; BSR (Bank select register); PCLATH(Write buffer for program counter PC<14:8>); interrupt control registerINTCON.

According to an embodiment, the microprocessor or microcontroller mayfurther comprise an interrupt control unit 105 which may be coupled withcertain special function registers 115. Upon occurrence of an interruptor any other induced context switch, such as software traps, thecontents of the following registers selected form the special functionregisters mapped to all memory banks are automatically saved. STATUS(except for TO and PD); BSR, PCLATH, WREG, FSR0 (Both FSR0H and FSR0L),and FSR1 (Both FSR1H and FSR1L). The registers are automaticallyrestored to their pre-interrupt values upon a return from interrupt.

To this end, as shown in FIG. 1, the microprocessor or microcontrollercore may have at least one additional set of registers 115 which willstore the content of the above mentioned registers. However, accordingto other embodiments, a stack, additional data memory, etc. may beprovided to store the content of these registers upon a context switch.

As shown in FIG. 2, the program counter PC consists of two concatenated8 bit registers PCL 230 and PCH 240. It addresses words in programmemory, and according to an embodiment, is e.g. 15 bits wide. Thus, itcan be used to address up to 32 kW. PCL 230, the low byte of the PC, ismapped in the data memory 160. Thus, it is common across all banks, andlocated for example at address 02h. PCL 240 is readable and writablejust as any other register. Any time that PCL 230 is modified by aninstruction, whether a write to PCL 230 or a read-modify-write, the CPUmay need to execute a forced NOP in order to retrieve the instruction atthe new address. PCH 240 is the high byte of the PC and is not directlyaddressable. Since PCH may not be mapped in data or program memory,register PCLATH 220 (PC high latch) is used as holding latches for thehigh bits of the PC (PCH<6:0>). According to an embodiment, PCLATH 220is mapped into data memory. Thus, it is common across all banks, and canbe located at address 0Ah. PCLATH 220 is only updated by explicitloading of the register. therefore, according to an embodiment no otherinstructions update it. The enhanced microcnotrolelr may be designedthat updating PCLATH 220 does not automatically update PCH 240. PCH 240is only updated with the content of PCLATH 220 on GOTO, CALL and CALLWinstructions. The PC is incremented by 1 after each instruction fetch onthe rising edge of Q1 unless: Modified by a GOTO, CALL, RETURN, RETLW,RETFIE, or Branch instruction; Modified by an interrupt response; Due todestination write to PCL by an instruction.

“Skips” are equivalent to a forced NOP cycle at the skipped address. Asshown in FIG. 2, the operations of the PC 230, 240 and PCLATH 220, fordifferent instructions are as follows:

Read instructions on PCL 230: PCL 230→□data bus 200→□ALU 170 ordestination.

Write instructions on PCL 230: 8-bit data

230.

Read-Modify-Write instructions on PCL 230: Any instruction that does aread-write-modify operation on PCL 230. Read: PCL 230→□data bus 200→□ALU170; Write: 8-bit result

data bus →□PCL RETURN instruction: TOS

14:0>

FIG. 3 shows in addition a fetched instruction 210 and its effect on theprogram counter 230, 240. FIG. 3 applies to the following instructions:

GOTO instruction: A destination address is provided in the 2-wordinstruction (opcode) 210. Opcode<7:0>

<10:8>→□PCH<2:0>240; PCLATH<6:3> 220 →□PCH<6:3>240.

CALL instruction: An 11-bit destination address is provided in theinstruction 210. Push the current address (PC+1) to the stack. Opcode<7:0> →□PCL <7:0> 230; Opcode <10:8>

<6:3> 220 →□PCH <6:3>240.

FIG. 4 shows the configuration for the following instructions: BRAinstruction: A 9-bit, signed, offset is provided in the instruction 210.Opcode <8:0>+PC(+1)→PC.

FIG. 5 shows the configuration for the following instructions: BRWinstruction: An 8-bit unsigned, offset provided in WREG 180. PC(+1)+WREG .→□PC

FIG. 6 shows the configuration for the following instructions: CALLWinstruction: An 8-bit destination address is provided in WREG 180. Pushthe current address (PC+1) to the stack. WREG<7:0>

□PCL <7:0> PCLATH <6:0>.→□PCH <6:0>

To enable a test memory area, the program counter 230, 240 may have ahidden 16th bit, PC<15>. When PC<15> is set the instructions will befetched from a test area. In user mode, PC<15> is always 0, and cannotbe modified in software. In test mode, PC<15> defaults to 0, but can beset by a “load configuration” command. It can be cleared by a “Reset PC”command. The test memory access may behave with an in circuit debugger(ICD) as follows:

ICD_v1: PC<15> is forced high to fetch the ICD vector, but returns to 0after the first instruction (GOTO ICD_ROUTINE) is executed. From thenuntil exiting the debug exec, PC<14:11> is forced to ‘1111b’, but PCLATHis not affected. ICD_v2: If the ICD debug exec is in user memory, thenit follows ICD_(—V)1. If the debug exec is in test memory, then PC<15>is forced high to fetch the ICD vector, and returns to zero on icdreturn.

The enhanced microcontroller devices according to various embodimentsmay support a stack memory 15 bits wide and 16 bits deep as shown inFIG. 7. During normal operation, the stack 310 is assumed to be 16 wordsdeep. In normal mode, no direct user access is provided to the stack310. The stack is not part of either the program or data memory space.The full PC (Program Counter) is pushed onto the stack when a CALL orCALLW instruction is executed, or an interrupt request is acknowledged.The PC value is pulled off the stack on a RETURN, RETLW, or RETFIE,instruction. PCLATH is not affected by any of the CALL or RETURN typeinstructions.

The stack 310 operates as a 16 word by 15-bit RAM and a 4-bit stackpointer. Incrementing/decrementing the pointer past 1111b/0000b willcause it to wrap around to 0000b/1111b. During a CALL type instruction,the stack pointer is incremented and the contents of the PC are loadedto the stack 310. During a RETURN type instruction the contents pointedto are transferred to the PC and then the stack pointer is decremented.The stack pointer is initialized to ‘1111b’ after all Resets. The firstcall will cause the pointer to wrap to 0000b.

A stack overflow/underflow event occurs when the stack pointer isincremented/decremented past 1111b/0000b AND a data transfer to/from thestack is conducted at the new address. An overflow event must not occuron the first CALL.

On the 16th consecutive call, the stack pointer will have a value of1111b. The 17th consecutive CALL will cause the stack pointer to wraparound to 0000b, and the PC to be loaded at this position. Thisconstitutes an overflow event. When the stack has been popped enoughtimes to reach 0000b, further popping will cause the contents at 0000bto be transferred to the PC, and the stack pointer to be decremented.The stack pointer will wrap to 1111b, this DOES NOT constitute anunderflow event. Only on the next consecutive pop, when data transferfrom 1111b is attempted, will an underflow event occur. In user mode, astack overflow or underflow will set the appropriate bit (STOF or STUF)in the PCON register, and cause a software reset.

When in ICD mode, the stack may have two segments. The normal user modestack is still 16 words deep, but a separate ICD stack may also beprovided. In ICD mode it will be possible to access the top of the stackand the stack pointer. In ICD mode, the top of the stack (TOS) isreadable and writable. Two register locations, TOSH and TOSL, willaddress the stack RAM location pointed to by the stack pointer (STKPTR).After a CALL type instruction, the software can read the pushed value byreading the TOSH and TOSL registers. These values can be placed on auser defined software stack. Writing to the TOS registers will cause thePC to be updated with the new value on the next RETURN type instruction.

The STKPTR register contains the stack pointer value. As previouslynoted, STKPTR is accessible in ICD mode only. In ICD mode, the stackpointer can be accessed through the STKPTR register. The user may readand write the stack pointer values. The stack pointer is initialized to‘1111b’ after all Resets. In ICD mode, an automatic software reset willnot be applied on an overflow/underflow event. However, the stackoverflow (STOF) or underflow (STUF) bit in the PCON register will stillbe set, allowing software verification of a stack condition. Because areset will not be executed on an underflow/overflow, the stack pointer(STKPTR) will not be reset. On an overflow/underflow the stack pointerwill wrap around and then resume normal operation. The user has to clearthe overflow (STOF) or underflow (STUF) bits explicitly—and they willagain be automatically set on subsequent overflows/underflows. StackOverflow/Underflow events can only be caused by an instruction thatmodifies the stack pointer using the stack pointer hardware.

This includes: CALL, TRAP; RETURN, RETFIE, RETLW; Any interrupt and ICDtraps. Instructions that modify the stack pointer through the ALU (ICDmode only) will not cause the stack underflow/overflow condition, andthus will not set the (STOF) or (STUF) bits. Examples are (ICD modeonly): INCF STKPTR; DECF STKPTR; ADDWF STKPTR.

When a device is reset, the PC is loaded with the Reset vector (0h). Thestack pointer is initialized to ‘1111b’, and the Top of Stack register(TOS) is ‘0000h’. A second push increments the stack pointer and thenloads the current PC into stack level. On the 16th consecutive call, thestack pointer will have a value of 1111b. The 17th consecutive CALL willcause the stack pointer to wrap around to 0000b, and the PC to be loadedat this position. This constitutes an overflow event. A RETURN pop willcopy the stack contents pointed to the PC and then decrement the stackpointer. When the stack has been popped enough times to reach 0000b,further popping will cause the contents at 0000b to be transferred tothe PC, and the stack pointer to be decremented. The stack pointer willwrap to 1111b, this DOES NOT constitute an underflow event. Only on thenext consecutive pop, when data transfer from 1111b is attempted, willan underflow event occur. In debug (ICD) mode a special instruction willcause the STKPTR to be incremented. The PC is not loaded to TOS. It isup to the user to make sure TOS is loaded with the appropriate databefore executing the INCF STKPTR instruction (this instruction is thusequivalent to a PUSH instruction. The DECF STKPTR instruction willdecrement the stack pointer, the PC is not loaded with the TOS value.

As shown in FIG. 8, the 15-bit program counter 400 is capable ofaddressing a 32k×14 bit program memory space. The program memory space430 primarily contains instructions for execution; however, data tablesmay be stored and accessed as well (using legacy program memoryread/write infrastructure, as well as the new functionality associatedwith indirect addressing, see the FSR section for more detail). There isalso a 16th PC bit hidden during normal operation, and when set, it ispossible to address another 32k×14 of memory reserved for configurationbits, the device ID, and test memory 440. This bit is only set in testmode or programming mode. As shown in FIG. 8, the Reset vector is at‘0000h’ and the interrupt vector is at ‘0004h’.

According to one embodiment, the enhanced microcontroller can addressdata memory 160 and general purpose RAM of up to 2048 bytes. The datamemory address bus is 11 bits wide. Data memory is partitioned into 16banks of 128 bytes each that contain the General Purpose Registers(GPRs) and Special Function Registers (SFRs). The bank is selected bythe bank select register (BSR<3:0>) as shown in FIG. 9. The BSR registercan access more than 16 banks; however, this may be only allowed in ICDmode to allow for a larger data space for the ICD registers. (In ICDmode 32 banks can be accessed). The bits BSR0 and BSR1 are also mappedinto the STATUS register as RP0 and RP1 respectively. This is to allowfor backward compatibility with existing devices. A read or write toBSR0/1 will affect RP0/1 and vice versa. FIG. 10 shows an example datamemory map.

When the core is operating with an ICD module or in another embodiment,the total number of banks may be expanded to 32 for 4096 totaladdresses. This is to allow the ICD registers to be mapped into the dataspace and not use any of the user memory map. This will only be enabledwhen the ICD module is enabled. The user will have no access to any bankgreater than Bank 15. Other configurations are possible according tovarious embodiments.

FIG. 11 shows an embodiment of indirect addressing scheme which is amode of addressing data memory where the data memory address in theinstruction is determined by another register. This can be useful fordata tables or stacks in the data/program memory. The value of the fileselect register (FSR) register 960 is used as the data memory address.The enhanced microcontroller has two 16-bit register pairs 960 forindirect addressing. These so called file select register pairs are:FSR0H and FSR0L; and FSR1H and FSR1L. The FSRs 960 are 16-bit registersand thus allow addressing of up to 65,536 locations. A single bit 965 inthese file select registers 960 can be used to determine whether anaccess to data memory 160 or program memory 120 will be performed. Tothis end, logic unit 930 forwards the content of file select register960 to either program memory address 910 or RAM address 920 foraccessing the respective memories.

Non-indirect addressing uses the respective content “File” of a fetchedinstruction 950 through multiplexer 940. Bank access are then performedthrough RAM address 920 wherein the bank address is provided by therespective bank access register to form a full address 920. As shown inFIG. 11, file select registers 960 are provided for indirect addressing.For indirect addressing, the output of multiplexer 940 provides the“File” address through the content of the respective file selectregister 960. If indirect addressing is selected, bit 15 indicated bynumeral 965 of each file select register 960 is used to determinewhether an access to program memory 120 through program memory address910 or to data memory 160 through data address 920 will be performed.Indirect addressing is initiated through a respective select signal (notshown) controlling multiplexer 940.

When FSRn<15> equals 0, data memory 160 is addressed. When FSRn<15> is1, program memory 120 is addressed. The data memory 160 is mapped intothe first half of this address space (0000h to 7FFFh). If FSRn<15> is 0,FSRn<10:0> points to data memory locations 000h to 7FFh. In this caseFSRn<11:14> is ignored. The program memory 120 is mapped into the upperhalf of this address space (8000h to FFFFh). If FSRn<15> is 1, thenFSRn<14:0> points to program memory addresses 0000h to 7FFFh. Insummary: Addresses 8000h and higher point to program memory. Addressesbelow 8000h point to data memory, with only the lower 11 bits used foraddress decoding.

In addition, there are virtual registers INDF0 and INDF1 (See FIG. 10),which are not physically implemented. Reading or writing to theseregisters activates indirect addressing, with the value in thecorresponding FSR register being the address of the data. If file INDF0(or INDF1) itself is read indirectly via an FSR, all ‘0’s are read (Zerobit is set). Similarly, if INDF0 (or INDF1) is written to indirectly,the operation will be equivalent to a NOP, and the STATUS bits are notaffected. Indirect writes to program memory space (FSRn<15>=1) will haveno effect, and will lead to the equivalent of a NOP being executed.Indirect reads from program memory space (FSRn<15>=1) will cause thefirst 8 bits of the program memory location to be transferred to thedestination register, the EEDATH/PMDATH will be updated with the upper 6bits. According to various embodiments, other mechanism may beimplemented to induce indirect addressing.

FIG. 12 shows a summary of all special function registers according toan embodiment as used in any bank n of the data memory.

FIGS. 13A and B show the instruction set wherein the enhancedinstructions using the architecture as explained above are explained indetail below.

ADDFSR Add Literal to FSRn: Syntax: ADDFSR n, k

Operands: −32≦k≦31

n ∈[0,1]

Operation: FSR(n)+k→FSR(n)

Status Affected: None Encoding: 11 0001 0nkk kkkk

Description: The signed 6-bit literal ‘k’ is added to the contents ofthe FSR specified by ‘n’. FSRn is limited to the range 0000h -FFFFh.Incrementing/decrementing it beyond these bounds will cause it to wraparound. Note that addresses 8000h and larger point to program memory.Addresses below 8000h point to data memory, with only the lower 11 bitsused for address decoding.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4 Decode Read FSRn’ Process Data Write to FSRn

Example: ADDFSR 1, 23h

-   -   Before Instruction FSR1=0FFh    -   After Instruction FSR1=0122h

ADDWFC ADD WREG and CARRY bit to f: Syntax: ADDWFC f {,d}

Operands: 0≦f≦127

-   -   d ∈[0,1]

Operation: (WREG)+(f)+(C)→dest

Status Affected: C, DC, Z

Encoding: 11 1101 dfff ffff

Description: Add WREG, the CARRY flag and data memory location ‘f’. If‘d’ is ‘0’, the result is placed in WREG. If ‘d’ is ‘1’, the result isplaced in data memory location ‘f’.

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4 Decode Read reg ‘f’ Process Data Write to destination

Example: ADDWFC REG, 0

-   -   Before Instruction CARRY bit=1        -   REG=02h        -   WREG=4Dh    -   After Instruction CARRY bit=0        -   REG=02h WR2EG=50h

ASRF Arithmetic Right Shift: Syntax: ASRF f {,d}

Operands: 0≦f≦127

-   -   d ∈[0,1]

Operation: (f<7>)→dest<7>

-   -   (f<7:1>)→dest<6:0>,    -   (f<0>)→C,

Status Affected: C, Z

Encoding: 11 0111 dfff ffff

Description: The contents of register ‘f’ are shifted one bit to theright through the CARRY flag. The MSb remains unchanged. If ‘d’ is ‘0’,the result is placed in WREG. If ‘d’ is ‘1’, the result is stored backin register ‘f’.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4 Decode Read reg ‘f’ Process Data Write to destination

Example: ASRF REG, 0

Before Instruction REG=1110 0110

C=1

After Instruction REG=1110 0110

WREG=1111 0011

C=0

BRA Relative Branch: Syntax: BRA k

Operands: −256≦k≦255

Operation: (PC)+k→PC

Status Affected: None

Encoding: 11 001k kkkk kkkk

Description: Add the 2's complement number ‘k’ to the PC. Since the PCwill have incremented to fetch the next instruction, the new addresswill be PC+1+k. This instruction is a two-cycle instruction.

Words: 1

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4 Decode Read literal ‘k’ Process Data Write to PC

No operation No operation No operation No operation

Example: 0023h BRA 005h

-   -   Before Instruction PC=address(0023h)    -   After Instruction PC=address(0029h)

BRW Relative Branch with WREG: Syntax: BRW

Operands: None

Operation: (PC)+(WREG)→PC

Status Affected: None

Encoding: 00 0000 0000 1011

Description: Add the contents of WREG (unsigned) to the PC. Since the PCwill have incremented to fetch the next instruction, the new addresswill be PC+1+(WREG). This instruction is a two-cycle instruction. Thecontents of WREG is treated as an unsigned number.

Words: 1

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4 Decode Read reg WREG Process Data Write to PC No operationNo operation No operation No operation

Example: 0024h BRW

-   -   Before Instruction PC=address(0024h)        -   WREG=85h    -   After Instruction PC=address(00AAh)

CALLW Subroutine Call With WREG: Syntax: CALLW

Operands: None

Operation: (PC)+1→TOS,

-   -   (WREG)→PC<7:0>,    -   (PCLATH<6:0>)→PC<14:8>

Status Affected: None

Encoding: 00 0000 0000 1010

Description: Subroutine call with WREG. First, the return address (PC+1)is pushed onto the return stack. Then, the contents of WREG is loadedinto PC<7:0>, and the contents of PCLATH into PC<14:8>. CALLW is atwo-cycle instruction.

Words: 1

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4 Decode Read register WREG Process Data Write to PC Nooperation No operation No operation No operation

Example: 0025h CALLW

-   -   Before Instruction PC=address (0025h)        -   WREG=1Ah        -   PCLATH=10h    -   After Instruction TOS=address (0026h)        -   PC=101Ah        -   WREG=1Ah        -   PCLATH=10h

LSLF Logical Left Shift: Syntax: LSLF f {,d}

Operands: 0≦f≦127

-   -   d ∈[0,1]

Operation: (f<7>)→C

-   -   (f<6:0>)→dest<7:1>    -   0→dest<0>

Status Affected: C, Z

Encoding: 11 0101 dfff ffff

Description: The contents of register ‘f’ are shifted one bit to theleft through the CARRY flag. A ‘0’ is shifted into the LSb. If ‘d’ is‘0’, the result is placed in WREG. If ‘d’ is ‘1’, the result is storedback in register ‘f’.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4 Decode Read reg ‘f’ Process Data Write to destination

Example: LSLF REG, 0

-   -   Before Instruction REG=1110 0110        -   C=0    -   After Instruction REG=1110 0110        -   WREG=1100 1100        -   C=1

LSRF Logical Right Shift: Syntax: LSRF f {,d}

Operands: 0≦f≦127

-   -   d ∈[0,1]

Operation: 0→dest<7>

-   -   (f<7:1>)→dest<6:0>,    -   (f<0>)→C,

Status Affected: C, Z

Encoding: 11 0110 dfff ffff

Description: The contents of register ‘f’ are shifted one bit to theright through the CARRY flag. A ‘0’ is shifted into the MSb. If ‘d’ is‘0’, the result is placed in WREG. If ‘d’ is ‘1’, the result is storedback in register ‘f’.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination

Example: LSRF REG, 0

-   -   Before Instruction REG=1110 0110        -   C=1    -   After Instruction REG=1110 0110        -   WREG=0111 0011        -   C=0

MOVIW Move INDFn to WREG, with pre/post increment/decrement

-   -   Syntax: MOVIW ++/−−FSRn++/−−    -   n ∈[0,1]

Operands:

Operation: INDFn→WREG

Apply pre/post increment/decrement operation to FSRn.

Status Affected: Z (Only if destination is WREG)

Encoding: 00 0000 0001 0nmm

MM Operation

00 ++FSRn

01 −−FSRn

10 FSRn++

11 FSRn−−

Description: This instruction is used to move data between one of theindirect registers (INDFn) and WREG. Before/after this move, the pointer(FSRn) is updated by pre/post incrementing/decrementing it. FSRn islimited to the range 0000h-FFFFh. Incrementing/decrementing it beyondthese bounds will cause it to wrap around. Note that addresses largerthan 7FFFh point to program memory. Addresses below 8000h point to datamemory, with only the lower 11 bits used for address decoding. Theincrement/decrement operation on FSRn WILL NOT affect any STATUS bits.This instruction can only affect the Z flag if a value of 00h is movedto WREG.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4 Decode Update pointer if Process Write to Read Source DataDestination register. register. Update pointer if needed.

Example: MOVIW FSR0++

-   -   Before Instruction FSR0=22h        -   WREG=FFh        -   (22h)=12h        -   (23h)=33h    -   After Instruction FSR0=23h        -   WREG=12h        -   (22h)=12h        -   (23h)=33h

Example: MOVIW ++FSR0

-   -   Before Instruction FSR0=22h        -   WREG=FFh        -   (22h)=12h        -   (23h)=33h    -   After Instruction FSR0=23h        -   WREG=33h        -   (22h)=12h        -   (23h)=33h

MOVIW Move INDFn to WREG, Indexed Indirect Addressing

-   -   Syntax: MOVIW [k]FSRn

Operands: −32≦k≦31

-   -   n c [0,1]

Operation: (FSRn+k)→WREG

Move data between location pointed to by FSRn+k and WREG.

Status Affected: Z (Only if destination is WREG)

Encoding: 11 1111 0nkk kkkk

Description: This instruction is used to move data between a locationpointed to by FSRn+k and WREG. FSRn is NOT updated with k. Theaddressable range is limited to 0000h-FFFFh. Indexing beyond thesebounds will cause an address wrap-around. Note that addresses 8000h andhigher point to program memory. Addresses below 8000h point to datamemory, with only the lower 11 bits used for address decoding. Addresscalculation (addition of k to FSRn) WILL NOT affect any STATUS bits.This instruction can only affect the Z flag if a value of 00h is movedto WREG.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4 Decode Address Calculation. Process Data Write to ReadSource register. Destination register.

Example: MOVIW [5]FSR0

-   -   Before Instruction FSR0=22h        -   WREG=FFh        -   (22h)=12h        -   (27h)=39h    -   After Instruction FSR0=22h        -   WREG=39h        -   (22h)=12h        -   (27h)=39h

Example: MOVIW [−5]FSR0

-   -   Before Instruction FSR0=22h        -   WREG=FFh        -   (1Dh)=17h        -   (22h)=12h    -   After Instruction FSR0=22h        -   WREG=17h        -   (1Dh)=17h        -   (22h)=12h

MOVLB Move literal to BSR: Syntax: MOVLB k

Operands: 0≦k≦15

Operation: k→BSR

Status Affected: None

Encoding: 00 0000 0010 kkkk

Description: The four-bit literal ‘1’ is loaded into the Bank SelectRegister (BSR).

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4 Decode Read literal ‘k’ Process Data Write literal ‘k’ toBSR

MOVLP Move literal to PCLATH: Syntax: MOVLP k

Operands: 0≦k≦127

Operation: k→PCLATH

Status Affected: None

Encoding: 11 0001 1kkk kkkk

Description: The seven-bit literal ‘k’ is loaded into the PCLATHregister.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4 Decode Read literal ‘k’ Process Data Write literal ‘k’ toPCLATH

MOVWI Indexed Indirect Move: Syntax: MOVWI [k]FSRn

Operands: −32≦k≦31

-   -   n ∈[0,1]

Operation: WREG→(FSRn+k)

Move data between WREG and location pointed to by FSRn+k.

Status Affected: Z (Only if destination is WREG)

Encoding: 11 1111 1nkk kkkk

Description: This instruction is used to move data between WREG and thelocation pointed to by FSRn+k. FSRn is NOT updated with k. Theaddressable range is limited to 0000h—FFFFh. Indexing beyond thesebounds will cause an address wrap-around. Note that addresses 8000h andhigher point to program memory. Addresses below 8000h point to datamemory, with only the lower 11 bits used for address decoding. Addresscalculation (addition of k to FSRn) WILL NOT affect any STATUS bits.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4 Decode Address Calculation. Process Data Write to ReadSource register. Destination register.

Example: MOVWI [3]FSR0

-   -   Before Instruction FSR0=22h        -   WREG=FFh        -   (22h)=12h        -   (25h)=56h    -   After Instruction FSR0=22h        -   WREG=FFh        -   (22h)=12h        -   (25h)=FFh

Example: MOVWI [−1]FSR0

-   -   Before Instruction FSR0=22h        -   WREG=FFh        -   (21h)=56h        -   (22h)=12h    -   After Instruction FSR0=22h        -   WREG=FFh        -   (21h)=FFh        -   (22h)=12h

Q Cycle Activity:

Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination

MOVWI Move WREG to INDFn, with pre/post increment/decrement

-   -   Syntax: MOVWI ++/−−FSRn++/−−

Operands:

-   -   n ∈[0,1]

Operation: WREG→INDFn

Apply pre/post increment/decrement operation to FSR used.

Status Affected: Z (Only if destination is WREG)

Encoding: 00 0000 0001 1nmm

MM Operations

00 ++FSRn

01 −−FSRn

10 FSRn++

11 FSRn−−

Description: This instruction is used to move data between WREG and oneof the indirect registers (INDFn). Before/after this move, the pointer(FSRn) is updated by pre/post incrementing/decrementing it. FSRn islimited to the range 0000h-FFFFh. Incrementing/decrementing it beyondthese bounds will cause it to wrap around. Note that addresses 8000h andhigher point to program memory. Addresses below 8000h point to datamemory, with only the lower 11 bits used for address decoding. Theincrement/decrement operation on FSRn WILL NOT affect any STATUS bits.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4 Decode Update pointer if Process Data Write to INDFn.needed. Update pointer if needed.

Example: MOVWI FSR0−−

-   -   Before Instruction FSR0=22h        -   WREG=FFh        -   (21h)=56h        -   (22h)=12h    -   After Instruction FSR0=21h        -   WREG=FFh        -   (21h)=56h        -   (22h)=FFh

Example: MOVWI −−FSR0

-   -   Before Instruction FSR0=22h        -   WREG=FFh        -   (21h)=56h        -   (22h)=12h    -   After Instruction FSR0=21h        -   WREG=FFh        -   (21h)=FFh        -   (22h)=12h

RESET Software Reset: Syntax: RESET

Operands: None

Operation: Execute nMCLR. Reset all registers and flags that areaffected by a MCLR Reset. Set PCON.nSWRST flag.

Status Affected: All

Encoding: 00 0000 0000 0001

Description: This instruction provides a way to execute a MCLR Reset bysoftware.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4 Decode Start Reset No operation No operation

Example: RESET

-   -   After Instruction Registers=Reset Value        -   Flags*=Reset Value

SUBWFB Subtract WREG from f with Borrow: Syntax: SUBWFB f {,d}

Operands: 0≦f≦127

-   -   d ∈[0,1]

Operation: (f)-(WREG)-(B)→dest

Status Affected: C, DC, Z

Encoding: 11 1011 dfff ffff

Description: Subtract WREG and the BORROW flag (CARRY) from register ‘f’(2's complement method). If ‘d’ is ‘0’, the result is stored in WREG. If‘d’ is ‘1’, the result is stored back in register ‘f’.

Words: 1

Cycles: 1

Example 1: SUBWFB REG, 1

-   -   Before Instruction REG=19h (0001 1001)        -   WREG=0Dh (0000 1101)        -   C=1 (So B=0)    -   After Instruction REG=0Ch (0000 1100)        -   WREG=0Dh (0000 1101)        -   C=1 (No Borrow)        -   DC=0 (Indicates a digit borrow)

Example 2: SUBWFB REG, 0

-   -   Before Instruction REG=1Bh (0001 1011)        -   WREG=1Ah (0001 1010)        -   C=0 (So B=1)    -   After Instruction REG=1Bh (0001 1011)        -   WREG=00h        -   C=1 (No Borrow)        -   DC=1 (No digit borrow)        -   Z=1 Result is zero

What is claimed is:
 1. A microprocessor or microcontroller devicecomprising: a central processing unit (CPU); a data memory coupled withthe CPU, wherein the data memory is divided into a plurality of memorybanks; and a plurality of special function registers and general purposeregisters which may be memory-mapped to said data memory, wherein atleast the following special function registers are memory-mapped to allmemory banks a status register, a bank select register, a plurality ofindirect memory address registers, a working register, and a programcounter high latch; and wherein upon occurrence of a context switch, theCPU is operable to automatically save the content of the statusregister, the bank select register, the plurality of indirect memoryaddress registers, the working register, and the program counter highlatch, and upon return from said context switch restores the content ofthe status register, the bank select register, the plurality of indirectmemory address registers, the working register, and the program counterhigh latch.
 2. The device according to claim 1, further comprising aninterrupt unit coupled with the CPU, wherein said context switch isinduced by an interrupt.
 3. The device according to claim 1, whereinsaid context switch is software induced.
 4. The device according toclaim 1, wherein the content of the status register, the bank selectregister, the plurality of indirect memory address registers, theworking register, and the program counter high latch is saved to aplurality of additional registers.
 5. The device according to claim 1,wherein the content of the status register, the bank select register,the plurality of indirect memory address registers, the workingregister, and the program counter high latch is saved to a stack oradditional memory.
 6. The device according to claim 1, wherein eachmemory bank has the following special function registers memory mapped:a plurality of indirect addressing mode registers which cause anindirect addressing access upon a read or write access to said first andsecond indirect addressing mode registers; a first program counterregister; a status register, a plurality of indirect memory addressregisters; a bank select register, a working register, a program counterhigh latch register, and an interrupt control register.
 7. The deviceaccording to claim 6, wherein said special function registers are mappedstarting at memory bank address
 0. 8. The device according to claim 7,comprising 2 indirect addressing mode registers and 4 indirect memoryaddress registers, wherein access to an indirect addressing moderegister uses 2 concatenated indirect memory address registers of said 4indirect memory address registers and wherein said special functionregisters are mapped from memory bank address 0 to 0Bh.
 9. The deviceaccording to claim 1, further comprising a program memory coupled withsaid CPU, wherein a bit in said indirect memory address registersindicates whether an indirect memory access is performed on said datamemory or said program memory.
 10. A method of operating amicroprocessor or microcontroller device comprising a central processingunit (CPU); a data memory coupled with the CPU, wherein the data memoryis divided into a plurality of memory banks; a plurality of specialfunction registers and general purpose registers, the method comprisingthe steps of: memory mapping at least the following special functionregisters to all memory banks: a status register, a bank selectregister, a plurality of indirect memory address registers, a workingregister, and a program counter high latch; upon occurrence of a contextswitch, saving automatically the content of the status register, thebank select register, the plurality of indirect memory addressregisters, the working register, and the program counter high latch, andupon return from said context switch restoring the content of the statusregister, the bank select register, the plurality of indirect memoryaddress registers, the working register, and the program counter highlatch.
 11. The method according to claim 10, further comprising inducingsaid context switch by an interrupt.
 12. The method according to claim10, wherein said context switch is software induced.
 13. The methodaccording to claim 10, wherein the content of the status register, thebank select register, the plurality of indirect memory addressregisters, the working register, and the program counter high latch issaved to a plurality of additional registers.
 14. The method accordingto claim 10, wherein the content of the status register, the bank selectregister, the plurality of indirect memory address registers, theworking register, and the program counter high latch is saved to a stackor additional memory.
 15. The method according to claim 10, wherein eachmemory bank has the following special function registers memory mapped:a plurality of indirect addressing mode registers which cause anindirect addressing access upon a read or write access to said first andsecond indirect addressing mode registers; a first program counterregister; a status register, a plurality of indirect memory addressregisters; a bank select register, a working register, a program counterhigh latch register, and an interrupt control register.
 16. The methodaccording to claim 15, wherein said special function registers aremapped starting at memory bank address
 0. 17. The method according toclaim 15, using 2 indirect addressing mode registers and 4 indirectmemory address registers, wherein access to an indirect addressing moderegister uses 2 concatenated indirect memory address registers of said 4indirect memory address registers and wherein said special functionregisters are mapped from memory bank address 0 to 0Bh.
 18. The methodaccording to claim 10, using a program memory coupled with said CPU,wherein a bit in said indirect memory address registers indicateswhether an indirect memory access is performed on said data memory orsaid program memory.